The present invention relates to an inspection method of a contact failure of a semiconductor device and to the semiconductor device to which this inspection method is applied.
Inspection of a semiconductor integrated circuit, the whole circuit being exposed on the surface of a substrate in the middle of a wiring work in the case of wiring within the same layer, can therefore involve using a variety of optical defect inspection methods. In the case of a failure of a contact hole for connecting multi-layered wirings, however, a defective portion might be invisible from the surface. Hence, an exact grasp of a failure occurrence rate of the contact portion requires utilizing an electrical characteristic of a contact chain portion thereof. Herein, the contact chain represents a pattern with which the wirings are connected in a chained configuration between two or more wiring layers. Electric inspection methods of this contact chain are generally a method (which will hereinafter be referred to as a contact inspection) of connecting an electrode directly to the wiring and a method that utilizes a voltage contrast test.
Implementation of the contact inspection in the middle of a manufacturing process involves some difficulty. Therefore, the contact inspections are generally conducted batchwise at a stage of completing a wafer process. In this case, however, there is a large time difference in feedback from an inspection result to a manufacturing line. Hence, the contact inspection is no more than providing stuff for judging a level of how a product is graded. On the other hand, the voltage contrast test can be conducted in a non-contact state with the surface of the product in the middle of the manufacturing process and has been therefore in the progress of its being utilized over the recent years. It is to be noted that the following Patent document 1 discloses the voltage contrast test.
[Patent document 1] Japanese Unexamined Patent Publication No. 2004-501505